CRb7 is called the Split Mode bit and is an override of CRb4 and CRb3. If CRb7 is set to a logical ‘1’, the device is in split mode. All microprocessor writes to the MT8980 in Split mode are to the Connection Memory Low. All microprocessor reads of the MT8980 in split mode are from Data Memory. If CRb7 is a logical ‘0’, memory block selection is determined by CRb4 and CRb3.

The last bit in the Control Register, CRb5, is unused. Also, when using the MT8981, CRb2 is unused. It is also important to note that CRb4 and CRb3 must never be set to ‘00’.

PROGRAMMING EXAMPLES

The way the control register, the memory blocks and the external address bits work together is clarified with several examples.

In the first example, the operation of reading information contained in Channel 5 of Input Stream 2 (STi2) through the microprocessor port is examined. To read ST-BUS input information, the microprocessor must read the Data Memory. Data Memory may be specified in the Control Register by either setting the Split Mode bit, CRb7, to a logical
‘1’, or by setting CRb4 and CRb3 to the binary state
‘01’.To access the portion of Data Memory
corresponding to STi2, CRb2, CRb1 and CRb0 must be set to ‘010’. CRb6 and CRb5 have no effect on this example. Once the Control Register bits are set up in this manner, the microprocessor can read the information contained in any of the channels of STi2 by keeping A5 high and using A4-A0 to determine which channel is to be read. To access Channel 5, A4-A0 must be set to ‘00101’.
Example two consists of switching Channel 31 on STi0 to Channel 1 on Output Stream 7 (STo7). In this case, the locations corresponding to Channel 1 on STo7 in the two Connection Memories have to be accessed. Connection Memory Low must contain the Data Memory address of the source channel. Connection Memory High specifies the mode of Channel 1 on STo7 and whether it is in a high impedance state or not. To access Connection
Memory Low, CRb4 and CRb3 must be set to ‘10’. To access STo7s’ 32 byte segment, CRb2, CRb1 and CRb0 must be set to ‘111’. CRb7 may be either a ‘1‘ or a ‘0’ for writes (if a ‘0’ then CRb4 and CRb3 must have been set properly). For reads, CRb7 must be a‘0’. If it was a ‘1’, then CRb4 and CRb3 would have been inconsequential and the read would have been from Data Memory. CRb6 and CRb5 do not affect the access of the Connection Memory Low byte. To access Channel 1, A4-A0 must be set to ‘00001’.