· INTERNAL SUTRUCTURE

There are four major functional blocks inside the MT8980. These blocks are the Data Memory, the Connection Memory High, the Connection Memory Low and the Control Register. Data Memory is related to the input ST-BUS streams; Connection Memory High and Connection Memory Low are related to the output ST-BUS streams. The Control Register performs block addressing functions and overall mode determination.

The Data Memory is where information is stored as it comes in from the ST-BUS inputs. The loading of information into Data Memory from the inputs is automatic (Data Memory may not be written into from the microprocessor port). Channel information is converted from the serial ST-BUS format into a parallel format and stored in a corresponding byte in the Data Memory in an unchanging sequence. The size of the MT8980’s Data Memory is 256 bytes and the size of the MT8981’s Data Memory is 128 bytes (one byte of Data Memory per input channel).

Information may be read from the Data Memory in two ways: through the microprocessor port, or by a sequence that places Data Memory contents into an ST-BUS output channel. For a microprocessor port access, the address of a location in Data Memory is formed by Control Register bits 2, 1 and 0 (CRb2, CRb1 and CRb0) and external address bits A4, A3, A2, A1 and A0. When information in Data Memory is destined for an ST-BUS output channel, the address for Data Memory is formed by the contents of the Connection Memory Low byte associated with the output channel. This latter type of Data Memory access can only occur when the output channel has been placed into Switching mode.